Major purpose:
* The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security. Major functions:
*Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high speed protocols– NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
*Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. Education/Experience/Licenses etc.:
*At least 3 year experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs
*Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
*Proficiency in VHDL and FPGA design/debug – Xilinx FPGA / Vivado
*Excellent Analytical/Debug skills
*Good verbal, written, and presentation skills
*US Citizenship required A PLUS for prior experience with:
*High Level Synthesis (HLS) with Vivado,
*Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
*Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)